Module Selection Using Manufacturing Information

| Since manufacturing processes inherently uctuate, LSI chips which are produced from the same design have di erent propagation delays. However, the di erence in delays caused by the the process uctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits di erence in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm nds the optimal module selection which would not have been explored without manufacturing information.